View NIS5232_5516511.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2012 october, 2012 ? rev. 0 1 publication order number: NIS5232/d NIS5232 series +12 volt electronic fuse the NIS5232 is a cost effective, resettable fuse which can greatly enhance the reliability of a hard drive or other circuit from both catastrophic and shutdown failures. it is designed to buffer the load device from excessive input voltage which can damage sensitive circuits. it also includes an overvoltage clamp circuit that limits the output voltage during transients but does not shut the unit down, thereby allowing the load circuit to continue operation. two thermal options are available, latching and auto ? retry. features ? integrated power device ? power device thermally protected ? no external current shunt required ? 9 v to 18 v input range ? 44 m typical ? internal charge pump ? internal undervoltage lockout circuit ? internal overvoltage clamp ? esd ratings: human body model (hbm); 1500 v machine model (mm); 200 v ? these devices are pb ? free and are rohs compliant typical applications ? hard drives ? mother board power management http://onsemi.com marking diagram dfn10 case 485c 232 ayw 1 232 = latching version 232h = auto ? retry version a = assembly location y = year w = work week = pb ? free package (note: microdot may be in either location) 4.2 amp, 12 volt electronic fuse pin function 1 gnd 2 dv/dt 3 enable/fault 4 ilimit 5nc 6 ? 10 source 11 (flag) vcc see detailed ordering and shipping information in the ordering information section on page 10 of this data sheet. ordering information www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 2 figure 1. block diagram enable/ fault source i limit dv/dt gnd vcc enable charge pump thermal shutdown uvlo current limit voltage clamp dv/dt control table 1. functional pin description pin function description 1 ground negative input voltage to the device. this is used as the internal reference for the ic. 2 dv/dt the internal dv/dt circuit controls the slew rate of the output voltage at turn on. it has an internal capacitor that allows it to ramp up over a period of 2 ms. an external capacitor can be added to this pin to increase the ramp time. if an additional time delay is not required, this pin should be left open. 3 enable/fault the enable/fault pin is a tri ? state, bidirectional interface. it can be used to enable or disable the output of the device by pulling it to ground using an open drain or open collector device. if a thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that the device is in thermal shutdown. it can also be connected to another device in this family to cause a simultaneous shutdown during thermal events. 4 i limit a resistor between this pin and the source pin sets the overload and short circuit current limit levels. 6 ? 10 source this pin is the source of the internal power fet and the output terminal of the fuse. 11 (belly pad) v cc positive input voltage to the device. maximum ratings rating symbol value unit input voltage, operating, steady ? state (v cc to gnd, note 1) transient (100 ms) v in ? 0.6 to 18 ? 0.6 to 25 v thermal resistance, junction ? to ? air 0.1 in 2 copper (note 2) 0.5 in 2 copper (note 2) 4 ? layer board (note 4) ja 160 95 50 c/w thermal resistance, junction ? to ? lead (pin 1) jl 27 c/w thermal resistance, junction ? to ? case jc 20 c/w total power dissipation @ t a = 25 c derate above 25 c p max 1.3 10.4 w mw/ c operating temperature range (note 3) t j ? 40 to 150 c nonoperating temperature range t j ? 55 to 155 c lead temperature, soldering (10 sec) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the p ackage. 2. 1 oz. copper, double ? sided fr4. 3. thermal limit is set above the maximum thermal rating. it is not recommended to operate this device at temperatures greater t han the maximum ratings for extended periods of time. 4. jesd51 ? 7 4 ? layer board. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 3 electrical characteristics (unless otherwise noted: v cc = 12 v, c l = 100 f, dv/dt pin open, r limit = 10 , t j = 25 c unless otherwise noted.) characteristics symbol min typ max unit power fet delay time (enabling of chip to i d = 100 ma with 1 a resistive load) t dly 220 s kelvin on resistance (note 5) t j = 140 c (note 6) r dson 35 44 62 55 m off state output voltage (v cc = 18 v dc , v gs = 0 v dc , r l = ) v off 190 300 mv output capacitance (v ds = 12 v dc , v gs = 0 v dc , f = 1 mhz) 250 pf continuous current (t a = 25 c, 0.5 in 2 copper) (note 6) (t a = 80 c, minimum copper) i d i d 4.2 2.5 a thermal latch shutdown temperature (note 6) t sd 150 175 200 c thermal hysteresis (decrease in die temperature for turn on, does not apply to latching parts) t hyst 45 c under/overvoltage protection output clamping voltage (overvoltage protection) (v cc = 18 v) v clamp 14 15 16.2 v undervoltage lockout (turn on, voltage going high) v uvlo 7.7 8.5 9.3 v uvlo hysteresis v hyst ? 0.80 ? v current limit kelvin short circuit current limit (r limit = 15.4 , note 7) i lim ? ss 2.75 3.44 4.25 a kelvin overload current limit (r limit = 15.4 , note 7) i lim ? ol 4.6 a dv/dt circuit output voltage ramp time (enable to v out = 11.7 v) t slew 0.5 0.9 1.8 ms maximum capacitor voltage v max v cc v enable/fault logic level low (output disabled) v in ? low 0.35 0.58 0.81 v logic level mid (thermal fault, output disabled) v in ? mid 0.82 1.4 1.95 v logic level high (output enabled) v in ? high 1.96 2.64 3.30 v high state maximum voltage v in ? max 3.40 4.30 5.2 v logic low sink current (v enable = 0 v) i in ? low ? 17 ? 25 a logic high leakage current for external switch (v enable = 3.3 v) i in ? leak 1.0 a maximum fanout for fault signal (total number of chips that can be connected to this pin for simultaneous shutdown) fan 3.0 units total device bias current (operational) i bias 1. 8 2.5 ma bias current (shutdown) i bias 1.0 ma minimum operating voltage (notes 6 and 8) v min 7.6 v 5. pulse test: pulse width 300 us, duty cycle 2%. 6. verified by design. 7. refer to explanation of short circuit and overload conditions in application note and8140. 8. device will shut down prior to reaching this level based on actual uvlo trip point. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 4 10 0 30 20 50 40 60 0.1 1 10 100 1000 10000 100000 power (w) time (ms) 25 c 80 c 50 c figure 2. power dissipation vs. thermal trip time figure 3. application circuit with direct current sensing load gnd enable +12 v r s NIS5232 source v cc enable/ fault i limit dv/dt gnd 10 9 8 7 6 4 11 3 12 figure 4. application circuit with kelvin current sensing load gnd enable +12 v r s NIS5232 source v cc enable/ fault i limit dv/dt gnd 10 9 8 7 6 4 11 3 12 www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 5 figure 5. common thermal shutdown source v cc enable/ fault i limit dv/dt gnd load enable r s load source v cc i limit enable/ fault dv/dt gnd nis5135 NIS5232 www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 6 7.4 7.6 7.8 8 8.2 8.4 8.6 8.8 9 ? 50 ? 25 0 25 50 75 100 125 150 temperature ( c) uvlo (v) figure 6. uvlo turn ? on 0.72 0.74 0.76 0.78 0.8 0.82 0.84 0.86 ? 50 ? 25 0 25 50 75 100 125 150 temperature ( c) figure 7. uvlo hysteresis hyst (v) 14.5 14.6 14.7 14.8 14.9 15 15.1 15.2 15.3 ? 50 ? 25 0 25 50 75 100 125 150 voltage (v) temperature ( c) figure 8. output clamping voltage 0.85 0.9 0.95 1 1.05 ? 50 ? 25 0 25 50 75 100 125 150 temperature ( c) figure 9. output voltage dv/dt rate ramp time (ms) figure 10. input transient response 0 400 800 1200 1600 0.5 0.6 0.7 0.8 current (ma) figure 11. body diode forward characteristics forward voltage (v) www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 7 4 5 6 7 8 9 0 0.5 1 1.5 2 current (a) figure 12. thermal limit vs. copper area and ambient temperature copper area (in 2 ) ? 40 c 0 c 25 c 50 c 85 c 0.1 1 10 10 100 1000 current (a) r limit ( ) figure 13. current limit vs. r sense for direct current sensing ol sc 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 ? 50 0 50 100 150 ol sc current (a) temperature ( c) figure 14. direct current sensing levels vs. temperature for 27 sense resistor 0.1 1 10 1 10 100 current (a) r sense ( ) ol sc figure 15. current limit vs. r sense for kelvin current sensing 3 3.5 4 4.5 5 5.5 6 ? 40 ? 20 0 20 40 60 80 100 current (a) temperature ( c) ol sc figure 16. kelvin current sensing levels vs. temperature for 15 sense resistor 1 1.5 2 2.5 3 3.5 4 ? 40 ? 200 2040608010 0 temperature ( c) ol sc figure 17. kelvin current sensing levels vs. temperature for 33 sense resistor current (a) www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 8 40 45 50 55 7.0 9.0 11 13 15 v cc (v) figure 18. on resistance vs. v cc on resistance (m ) application information basic operation this device is a self ? protected, resettable, electronic fuse. it contains circuits to monitor the input voltage, output voltage, output current and die temperature. on application of the input voltage, the device will apply the input voltage to the load based on the restrictions of the controlling circuits. the dv/dt of the output voltage will be controlled by the internal dv/dt circuit. the output voltage will slew from 0 v to the rated output voltage in 2 ms, unless additional capacitance is added to the dv/dt pin. the device will remain on as long as the temperature does not exceed the 175 c limit that is programmed into the chip. the current limit circuit does not shut down the part but will reduce the conductivity of the fet to maintain a constant current at the internally set current limit level. the input overvoltage clamp also does not shutdown the part, but will limit the output voltage to 15 v in the event that the input exceeds that level. an internal charge pump provides bias for the gate voltage of the internal n ? channel power fet and also for the current limit circuit. the remainder of the control circuitry operates between the input voltage (v cc ) and ground. current limit the current limit circuit uses a sensefet along with a reference and amplifier to control the peak current in the device. the sensefet allows for a small fraction of the load current to be measured, which has the advantage of reducing the losses in the sense resistor as well as increasing the value and decreasing the power rating of the sense resistor. sense resistors are typically in the tens of ohms range with power ratings of several milliwatts making them very inexpensive chip resistors. the current limit circuit has two limiting values, one for short circuit events which are defined as the mode of operation in which the gate is high and the fet is fully enhanced. the overload mode of operation occurs when the device is actively limiting the current and the gate is at an intermediate level. for a more detailed description of this circuit please refer to application note and8140. there are two methods of biasing the current limit circuit for this device. they are shown in the two application figures. direct current sensing connects the sense resistor between the current limit pin and the load. this method includes the bond wire resistance in the current limit circuit. this resistance has an impact on the current limit levels for a given resistor and may vary slightly depending on the impedance between the sense resistor and the source pins. the on resistance of the device will be slightly lower in this configuration since all five source pins are connected in parallel and therefore, the effective bond wire resistance is one fifth of the resistance for any given pin. the other method is kelvin sensing. this method uses one of the source pins as the connection for the current sense resistor. this connection senses the voltage on the die and therefore any bond wire resistance and external impedance on the board have no effect on the current limit levels. in this configuration the on resistance is slightly increased relative to the direct sense method since only for of the source pins are used for power. overvoltage clamp the overvoltage clamp consists of an amplifier and reference. it monitors the output voltage and if the input voltage exceeds 15 v, the gate drive of the main fet is reduced to limit the output. this is intended to allow operation through transients while protecting the load. if an overvoltage condition exists for many seconds, the device may overheat due to the voltage drop across the fet combined with the load current. in this event, the thermal protection circuit would shut down the device. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 9 undervoltage lockout the undervoltage lockout circuit uses a comparator with hysteresis to monitor the input voltage. if the input voltage drops below the specified level, the output switch will be switched to a high impedance state. dv/dt circuit the dv/dt circuit brings the output voltage up under a linear, controlled rate regardless of the load impedance characteristics. an internal ramp generator creates a linear ramp, and a control circuit forces the output voltage to follow that ramp, scaled by a factor. the default ramp time is approximately 2 ms. this can be modified by adding an external capacitor at the dv/dt pin. this pin includes an internal current source of approximately 85 na. since the current level is very low, it is important to use a ceramic cap or other low leakage capacitor. aluminum electrolytic capacitors are not recommended for this circuit. the ramp time from 0 to the nominal output voltage can be determined by the following equation, where t is in seconds: t 0 12 24e6 50 pf c ext c ext t 0 ? 12 24e6 50 pf where: c is in farads t is in seconds any time that the unit shuts down due to a fault, enable shut ? down, or recycling of input power, the timing capacitor will be discharged and the output voltage will ramp from 0 at turn on. enable/fault the enable/fault pin is a multi ? function, bidirectional pin that can control the output of the chip as well as send information to other devices regarding the state of the chip. when this pin is low, the output of the fuse will be turned off. when this pin is high the output of the fuse will be turned ? on. if a thermal fault occurs, this pin will be pulled low to an intermediate level by an internal circuit. to use as a simple enable pin, an open drain or open collector device should be connected to this pin. due to its tri ? state operation, it should not be connected to any type of logic with an internal pullup device. if the chip shuts down due to the die temperature reaching its thermal limit, this pin will be pulled down to an intermediate level. this signal can be monitored by an external circuit to communicate that a thermal shutdown has occurred. if this pin is tied to another device in this family (NIS5232 or nis5135), a thermal shutdown of one device will cause both devices to disable their outputs. both devices will turn on once the fault is removed for the auto ? retry devices. for the latching thermal device, the outputs will be enabled after the enable pin has been pulled to ground with an external switch and then allowed to go high or after the input power has been recycled. for the auto retry devices, both devices will restart as soon as the die temperature of the device in shutdown has been reduced to the lower thermal limit. the thermal options are listed in the ordering table. thermal protection the NIS5232 includes an internal temperature sensing circuit that senses the temperature on the die of the power fet. if the temperature reaches 175 c, the device will shut down, and remove power from the load. output power can be restored by either recycling the input power or toggling the enable pin. power will automatically be reapplied to the load for auto ? retry devices once the die temperature has been reduced by 45 c. the thermal limit has been set high intentionally, to increase the trip time during high power transient events. it is not recommended to operate this device above 150 c for extended periods of time. figure 19. fault/enable signal levels www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 10 figure 20. enable/fault simplified circuit ? + ? + startup blanking thermal shutdown sd 1.4 v thermal reset enable sd 2.64 v enable/fault 4.3 v thermal sd 12 a 0.58 v ordering information device features package shipping ? NIS5232mn1txg thermal latching dfn10 (pb ? free) 3000 / tape & reel NIS5232mn2txg thermal auto ? retry dfn10 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NIS5232 series http://onsemi.com 11 package dimensions dfn10, 3 x 3, 0.5p case 485c ? 01 issue b 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intelle ctual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising ou t of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary ove r time. all operating parameters , including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NIS5232/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative www.datasheet.net/ datasheet pdf - http://www..co.kr/

▲Up To Search▲

Price & Availability of NIS5232

	To Download NIS5232 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .